Analog to Digital Converters are used in a wide variety of applications in the electronics industry, such as in digital television processing and in the conversion of analogue video onto DVD's. One type of ADC which is commonly used is a pipeline ADC. This ADC requires less components than that required by a flash ADC to carry out the same digital conversion. A pipeline ADC generally also performs a conversion quicker than a SAR converter, as in a SAR converter the conversion time is proportional to the number of bits to be converted. Consequently, a pipeline ADC is often favoured in applications where both a relatively fast conversion time is required and where the number of circuit components is to be kept to a minimum.
One of the main drawbacks of pipeline Analog to Digital Converters is that they are prone to architecture dependent integral non linearity (INL) errors. These errors are due to non-linearities present in the ADC, and manifest themselves as a curve in the output digital signal. Ideally, an INL curve would have all zero values, so that the resulting digital conversion would be an error free signal.
These INL errors are caused by a variety of sources, such as capacitor mismatch, stage gain errors and incomplete settling at higher sample rates (effectively dynamic gain errors). Each INL curve has a form specific to the topology of the pipeline ADC associated with it. For a pipeline ADC with a multi-bit first stage, the INL curve will have a periodic form, with the number of cycles corresponding to the number of decision levels in the first stage.
The table below shows typical parameters for an ADC when operating at 54 MS/s and 110 MS/s.
Present ADC Typical SpecificationsParameter54 MS/s Operation110 MS/s OperationUnitsResolution1210bitsINL  +/−5 (12 bit)  +/−5 (10 bit)LSBsDNL+1/−0.5 (12 bit)+1/−0.5 (10 bit)LSBsSINADFin = 1 MHz6357dBFin = 6 MHz6155dBFin = 15 MHz5753dBSNR (to6560dBNyquist)Input Range−1.2 to +1.2−1.2 to +1.2V diffSupply Voltage3.33.3VSupply Current4045mA(Including SHA)
These ADC specifications, although reasonable for the size and power dissipated, when used in applications such as video applications result in errors which manifest themselves as low frequency artefacts which are visible. The errors appear as an INL curve in the output converted signal. The nature of video applications means that linearity errors tend to be most visible when a signal with low frequency content is being processed, as it has been found that the human eye is very sensitive to low frequency errors in a video picture.
A typical INL curve can be seen in the graph of FIG. 1, for a pipeline ADC with a 4 bit 1st stage. It can be seen from this graph that the amplitude of the short term deviations which are superimposed on the INL curve increase with sample frequency. This is mainly due to the incomplete settling out of the 1st stage MDAC. This occurs when for example the gain of the first stage MDAC amplifier for this ADC does not result in its correct value. If the gain is not correct, then the output of the MDAC (i.e. the residue) which is passed to the rest of the ADC will under represent the true residue, and will accordingly result in an INL error. In cases where the gain is correct, but where the amplifier has insufficient time to settle to the correct final value, the effect will also appear like a gain error and give a corresponding INL error. The circumstance in which insufficient time is allowed for settling out of the MDAC arises when the sample rate is too high.
FIG. 2 illustrates the effect integral non-linearity errors have on a pipeline ADC with a multibit 1st stage when processing a video signal. For a slowly varying video signal, such as a signal that gradually ramps from black to white across the screen, it can be seen that the INL curve sawtooth creates a low frequency error on the video signal. For the black to white ramp, this is clearly visible as vertical bands in the picture. As a result, an imperfect video out signal is produced.
Consequently, it is desirable in applications such as video applications that particular attention be paid to eliminating low frequency artefacts in order to provide the best possible quality of output signal. However, the characteristic INL curve of a pipeline ADC makes these errors difficult to eliminate without expending a lot of power and area (more power and area gives quicker amplifier settling).
One method which has been used to reduce the effects of the INL curve is to dither the analog input with random noise, in order to mask the quantization noise. Another method involves dithering the analog input with random noise and removing the noise in the digital domain to correct for differential non-linearity (DNL) errors. The drawback of adding random noise is that in order to reduce the INL error, the noise must be of an amplitude sufficient to result in the output waveform changing from a staircase-like waveform (as a result of the errors), to that approaching the ideal waveform (a ramp). This value of amplitude is generally quite significant.
Another method which has been used to overcome the above outlined problems is to use a dithering scheme for video ADCs. The video signal is dithered with random noise at the video line rate and the dither is removed after digitisation. The effect of this is to make the INL errors unobvious to the eye, by placing them at a different point on each video scan line. However, this method does not actually eliminate the INL errors. Each line still has the error, but in a different place to the previous line. The error is in fact only hidden by the “vertical” filtering of the eye.
A further well known technique for removing INL errors involves dynamic element matching (DEM). This uses randomisation of the order of usage of the capacitor elements in the 1st stage MDAC of a pipeline ADC. In this technique, a 4 bit MDAC uses capacitors and an amplifier to implement the function Vout=8 *(Vin−D*Vref/16) where D is in the range 0 to 15. 16 capacitors are used to couple Vref or zero in the above equation. This technique compensates for the case where capacitors don't match (for example, if there is a capacitor which is larger than the other capacitors), which would generally result in some values of D having more weight, and consequently steps appearing in the ramp transfer function. In DEM, advantage is taken of the fact that the error caused by this capacitor would occur in the same place in a ramp signal applied to the ADC. The technique therefore rotates the capacitor usage so that the same capacitor is not used in the same position each time. As a result, the error moves about rapidly and is thus not noticeable to the human eye. However this technique only addresses the INL errors due to capacitor mismatch, and not those due to settling or gain errors, which are, in fact, more pronounced.
There therefore exists a need to provide an improved method for correcting INL curves in a pipeline ADC.